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Pull requests: llvm/circt

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Pull requests list

[FIRRTL] Fix bug in the the port pruner reduction
#10040 opened Mar 26, 2026 by seldridge • Draft
[FIRRTL] Return ArrayRef from getPortNamesAttr in FInstanceLike
#10039 opened Mar 25, 2026 by uenoku Loading…
[CI] Try workaround concurrency bug
#10038 opened Mar 25, 2026 by uenoku • Draft
1
[FIRRTL] Improve domain port naming in InferDomains pass
#10037 opened Mar 25, 2026 by seldridge • Draft
[Support] [FunctionalReduction] Add optional CaDiCaL dependency and SAT solver backend
#10032 opened Mar 25, 2026 by uenoku Loading…
4
[ExportVerilog] Add ModportType support for non-extern hw.module ports
#10030 opened Mar 25, 2026 by dmlockhart Loading…
2
[ExportVerilog] Fix XMR paths for inner symbols in generate.case (#9972)
#10025 opened Mar 24, 2026 by Salmooo Loading…
10
[FIRRTL] Invalids as constants in InferDomains
#10022 opened Mar 24, 2026 by seldridge • Draft
1
[Synth] Add canonicalization for synth.choice
#10019 opened Mar 23, 2026 by joaovam Loading…
1
14
[Synth] Canonicalize transitive choice operands
#10015 opened Mar 23, 2026 by AayushMainali-Github Loading…
Bump LLVM
#10010 opened Mar 22, 2026 by uenoku Loading…
4
[Synth] Extend functional reduction SAT support to OR/XOR/MIG
#10009 opened Mar 22, 2026 by uenoku Loading…
2
[HW] Add IMDCE module rewrites
#10007 opened Mar 22, 2026 by stomfaig Loading…
3
[HWFlattenModules] Add support for verif.formal parent ops.
#9984 opened Mar 19, 2026 by dobios • Draft
2
[RTG][circt-tblgen] Use config vars for include paths RTG Involving the `rtg` dialect
#9982 opened Mar 19, 2026 by maerhart Loading…
1
1
[Handshake] Fix argument index tracking with multiple ext memref args
#9978 opened Mar 19, 2026 by TopiLeppanen Loading…
1
[Sim][SimToSv] DPI-C Semantic preserving sim.func.dpi and sim.func.dpi.call
#9977 opened Mar 19, 2026 by pscabot Loading…
4
[FIRRTL] Emit memory initialization metadata FIRRTL Involving the `firrtl` dialect
#9974 opened Mar 18, 2026 by fzi-hielscher Loading…
1
[Datapath] Implement Add with Carry-In to Improve Subtraction Circuit Implementation
#9949 opened Mar 16, 2026 by sarthakmangla1 • Draft
1 task
8
[ImportVerilog][Sim] Added remaining Moore instructions for dynamic arrays, as well as the corresponding Sim dialect instructions
#9944 opened Mar 15, 2026 by yuriyKulinchenko Loading…
[FIRRTLToHW] Fix crash when lowering instance_choice with clock outputs
#9941 opened Mar 14, 2026 by seldridge • Draft
3
[LTL] Make ltl.delay support optional clocking
#9869 opened Mar 7, 2026 by Clo91eaf Loading…
12
[FIRRTL] Support probe ports in instance_choice operations
#9815 opened Mar 3, 2026 by uenoku • Draft
1
[circt-bmc] Add multi-clock BMC support via independent toggling
#9803 opened Mar 1, 2026 by robert-at-pretension-io • Draft
[circt-bmc] Add verif.contract support
#9800 opened Mar 1, 2026 by robert-at-pretension-io • Draft
1
ProTip! Updated in the last three days: updated:>2026-03-22.