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Pull requests: llvm/circt
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[FIRRTL] Return ArrayRef from getPortNamesAttr in FInstanceLike
#10039
opened Mar 25, 2026 by
uenoku
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[Support] [FunctionalReduction] Add optional CaDiCaL dependency and SAT solver backend
#10032
opened Mar 25, 2026 by
uenoku
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[ExportVerilog] Add ModportType support for non-extern hw.module ports
#10030
opened Mar 25, 2026 by
dmlockhart
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[ExportVerilog] Fix XMR paths for inner symbols in generate.case (#9972)
#10025
opened Mar 24, 2026 by
Salmooo
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[Synth] Canonicalize transitive choice operands
#10015
opened Mar 23, 2026 by
AayushMainali-Github
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[Synth] Extend functional reduction SAT support to OR/XOR/MIG
#10009
opened Mar 22, 2026 by
uenoku
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[RTG][circt-tblgen] Use config vars for include paths
RTG
Involving the `rtg` dialect
#9982
opened Mar 19, 2026 by
maerhart
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[Handshake] Fix argument index tracking with multiple ext memref args
#9978
opened Mar 19, 2026 by
TopiLeppanen
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[Sim][SimToSv] DPI-C Semantic preserving sim.func.dpi and sim.func.dpi.call
#9977
opened Mar 19, 2026 by
pscabot
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[FIRRTL] Emit memory initialization metadata
FIRRTL
Involving the `firrtl` dialect
#9974
opened Mar 18, 2026 by
fzi-hielscher
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[Datapath] Implement Add with Carry-In to Improve Subtraction Circuit Implementation
#9949
opened Mar 16, 2026 by
sarthakmangla1
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[ImportVerilog][Sim] Added remaining Moore instructions for dynamic arrays, as well as the corresponding Sim dialect instructions
#9944
opened Mar 15, 2026 by
yuriyKulinchenko
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[circt-bmc] Add multi-clock BMC support via independent toggling
#9803
opened Mar 1, 2026 by
robert-at-pretension-io
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Updated in the last three days: updated:>2026-03-22.